The present invention relates to a testing board for semiconductor memories, method of testing semiconductor memories and a method of manufacturing semiconductor memories and more particularly to technique effective for application to a testing board in which a testing circuit using an ALPG (Algorithmic Memory Pattern Generator) and sockets used to mount semiconductor memories on the testing board as devices to be tested are mounted, a testing method using the testing board and a manufacturing method of semiconductor memories.
Heretofore, a test for semiconductor memories such as RAMs (Random Access Memories) is carried out by a testing apparatus named a memory tester. The memory tester generates a test pattern (address and data) and supplies the semiconductor memories to be tested with the test pattern to be written in memory cells of the semiconductor memories. Then, data written in the memory cells are read out by the memory tester, so that the read-out data are compared with expected values within the memory tester to judge whether the data are identical with the expected values so that the semiconductor memories are diagnosed.
Procedure from manufacture to shipping of semiconductor memories is generally made as shown in FIG. 11. That is, after a plurality of semiconductor memories have been formed on a wafer in a semiconductor manufacturing process, probes come into contact with pads of the semiconductor memories being formed on the wafer to supply test signals thereto and receive output signals in response to the test signals so that the test using the probes is performed (step S11). The semiconductor memories are classified into repairable devices and non-repairable devices on the basis of the test result. With respect to the repairable devices, a redundant circuit provided within each memory is used to replace a defective bit with a spare memory cell (step S12).
Next, the wafer in which the plurality of semiconductor memories are formed is cut into respective chips and each chip is enclosed or sealed by means of resin to be assembled into a package (step S13). The semiconductor memories each assembled into the package are subjected to a high-temperature test (burn-in test) by means of a burn-in apparatus and to a low-speed operation test (long test) by means of a signal such as a clock having a low operation frequency to thereby remove a device having unstable operation on the basis of the test result (steps S14 and S15).
Then, a high-speed memory tester is used to perform a DC test for testing whether the semiconductor memories have a desired DC voltage characteristic by applying a DC voltage to the semiconductor memories, a function test for testing whether circuits are operated normally at usual operation speed with original operation frequency signals, and a timing test for testing whether a set-up time and a hold time of the semiconductor memories satisfy design specification successively (steps S16, S17′ and S18).
The semiconductor memories regarded as non-defective devices are used to assemble a memory module. The memory module is mounted on a mother board of a computer and is subjected to a selection test by means of an actual machine. Only the memory module judged as a normally operated module is shipped as a product (step S19 and S20′).
In the prior art as described above, since the test performed using the memory tester has a lot of test items, there is a problem that the test time is increased and a cost required for the test is increased. In other words, since the number of memories capable of being tested by the memory tester is very small as compared with the burn-in apparatus or the like, the test time is very increased if all of memories are to be tested by means of the limited number of memory testers and since the number of memory testers must be increased if the test is to be completed in a short time, the cost of equipment is very increased.
Further, since the test using the tester is made in accordance with a test pattern having the regularity according to a predetermined algorithm, any defective memory can be sometimes detected even from the memories judged as non-defective devices in the test using the tester if the memories are subjected to the test using a random test pattern. Accordingly, in the conventional test method using the tester, even when the test has been performed using the expensive tester at great pains, it is disadvantageous that the test using the random test pattern must be performed by the actual machine again after the memories have been assembled in a module.
On the other hand, there is proposed an invention that a testing circuit including a test pattern generator named ALPG for generating a memory test pattern in accordance with a predetermined algorithm is mounted in a memory chip to test a memory array by itself so that the frequency in use of the memory tester can be reduced (International Publication WO 98/47152). However, when the ALPG is mounted in the memory chip as in the above invention, it is disadvantageous that the yield is reduced due to a defect of the ALPG itself and the size of the memory chip is increased.
In this connection, the specification of the above invention discloses that the testing circuit having the above-mentioned configuration is structured as a semiconductor integrated circuit separated from the memory chip and the semiconductor integrated circuit and the memory chips are mounted on a board so that the self-test thereof can be realized even in the assembled state in a memory module. However, even the publication of the above invention does not quite disclose the test using a random pattern.